Conductive elements with adjacent, mutually adhered regions and semiconductor device assemblies including such conductive elements

ABSTRACT

Conductive elements that include a plurality of adjacent, mutually adhered regions are disclosed. All of the regions may include the same type of material. At least a portion of such a conductive element may be configured to extend laterally. In a semiconductor device assembly, such a conductive element is in electrical communication with a contact of at least one semiconductor device component, and may extend between corresponding contacts of two or more semiconductor device components.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 09/511,986,filed Feb. 24, 2000, pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to conductive elements for electricallyconnecting different semiconductor device components to one another.Particularly, the present invention relates to conductive elements thatare carried by semiconductor devices. More particularly, the presentinvention relates to stereolithographically fabricated conductiveelements. The present invention also relates to the conductive lines ofcarrier substrates, such as circuit boards, and to methods offabricating such carrier substrates.

2. State of the Art

Intermediate Conductive Elements. An electronic device typicallyincludes one or more semiconductor devices. The semiconductor devices ofan electronic device are electrically connected to a carrier substrate,which, in turn, electrically connects each semiconductor device to othercomponents of the electronic device. In order to fulfill the demands forelectronic devices of ever-decreasing size and ever-increasingcapability, much of the large, space-consuming circuitry components ofconventional electronic devices have been incorporated intosemiconductor devices. As a result, many state of the art electronicdevices include semiconductor devices that are directly connected to oneanother.

Conventionally, electrical connections between a semiconductor deviceand a carrier substrate or another semiconductor device are made by wayof wire bonds between bond pads of the semiconductor device and contactpads of the carrier substrate. Wire bonding is somewhat undesirable,however, in that the wire bonds are separately and sequentially formed.As state of the art semiconductor devices typically include largenumbers of bond pads positioned closely to one another, wire bondingthese semiconductor devices to carrier substrates or other semiconductordevices can be a very time-consuming process.

The semiconductor devices of many state of the art electronic devicesare connected to carrier substrates or other semiconductor devices withalternative types of intermediate conductive elements. For example,semiconductor devices can be flip-chip bonded, or bonded by way of acontrolled collapse chip connection (C-4) to a substrate or anothersemiconductor device with conductive structures, such as solder balls.When flip-chip type bonds are used, a minimal amount of the real estateon a carrier substrate or other semiconductor device component isconsumed.

Tape automated bonding (TAB) processes, which employ a tape including adielectric film with conductive traces extending thereacross, have alsobeen used to electrically connect semiconductor devices to othersemiconductor device components. Tape automated bonding is useful forforming very thin assemblies of semiconductor devices and substrates.

While all of the bond pads of a semiconductor device may besimultaneously connected with a carrier substrate or anothersemiconductor device when both flip-chip type bonding and TAB are used,neither of these techniques addresses the need for assemblies of bothminimal lateral dimensions and minimal thickness.

Circuit Boards: Circuit boards are often assembled with semiconductordevices to electrically connect different semiconductor devices to oneanother or to other components of an electronic device. Typically,circuit boards have one or more layers of metal circuitry carried by theinsulating, or dielectric, substrates thereof. When circuit boards haveconductive circuits extending across more than one plane thereof, thecircuits may be electrically connected by way of through holes that aremetal plated or filled.

Typically, reinforced polymeric materials are employed as the dielectricsubstrates of rigid circuit boards. The most commonly used dielectricsubstrate material is glass-reinforced epoxy. Some circuit boards aremade from polyimide resins so as to withstand higher temperatures. Otherdielectric materials have also been developed and used to fabricate thedielectric substrates of circuit boards.

Some applications require that the dielectric substrate of the circuitboard bend or flex during assembly of the circuit board withsemiconductor or other electronic devices or while a device includingthe circuit board is being used. While some flexible circuit boards havesubstrates fabricated from flexible dielectric materials that arereinforced with woven or random fibers, unsupported polymeric films mayalso be used to form the substrates of flexible circuit boards.

Conventional printed circuit boards having a single-layered substrateare machined to define the edges thereof, to bevel the edges thereof,and to form through holes at desired locations. Metal conductivecircuits are then formed on one or both surfaces of the printed circuitboards, in communication with metal plating or vias located in thethrough holes. Originally, conductive materials, such as silver, wereprinted onto the substrate to form the metal conductive circuits and toplate the through holes or to form vias therein.

Copper-clad laminates, which include a layer of copper secured to adielectric substrate, can also be used to fabricate circuit boards.Copper is removed from regions of the surface of the substrate whereconductive circuits are not desired. Accordingly, the process isreferred to as a “subtractive” technique.

Other conventional techniques for forming metal conductive circuits andplating or filling the through holes include electroless plating,electrolytic plating, and plasma-assisted chemical vapor deposition(“CVD”) processes. Etching processes may also be used to pattern theconductive circuits of printed circuit boards. As the metal circuits,plating, or vias are formed on the substrate, these processes arereferred to as “additive” techniques.

The substrates of state of the art circuit boards have multiple,laminated layers. The conductive circuits of these circuit boardslaterally traverse the surfaces of the boards, as well as severaldifferent planes through the interior of the substrate to accommodatethe increasingly complex semiconductor devices connected to thesubstrate while maintaining or decreasing the size of the circuit board.In manufacturing such boards, circuit traces are fabricated, as notedabove, on one layer of the substrate prior to laminating the next layerof the substrate thereto. Thus, laminated circuit boards are built up,layer by layer. The use of conventional processes to fabricatemultilayer circuit boards is, however, somewhat undesirable since eachnew layer must be aligned with every previously formed layer of thecircuit board to provide the desired functionality.

Completed circuit boards may then be tested. Optical or electricaltesting may be conducted to determine whether the circuit boards willfunction properly.

Circuit boards are typically fabricated on a very large scale, withsheets of several circuit boards typically being supplied tosemiconductor device manufacturers or electronic device manufacturersfor assembly with semiconductor devices and other electronic components.Conventional, large scale circuit board fabrication processes aretypically not useful for fabricating prototype circuit boards.

When a new circuit board design is needed, a prototype circuit board isusually fabricated. Due to the complexity of state of the artsemiconductor devices and electronic devices, the fabrication ofprototype circuit boards is a very time-consuming process. Moreover,production scale circuit boards based on a certain prototype circuitboard design may not provide the same electrical performance asintended.

Accordingly, there is a need for a method that can be employed toquickly fabricate simple and multilayered circuit boards in either verysmall numbers or very large numbers. There is also a need for a processfor fabricating multilayered circuit boards that does not requirerepeated alignment of each of the new layers of the circuit board withthe previously fabricated layers thereof.

Stereolithography. In the past decade, a manufacturing technique termed“stereolithography,” also known as “layered manufacturing,” has evolvedto a degree where it is employed in many industries.

Essentially, stereolithography as conventionally practiced involvesutilizing a computer to generate a three-dimensional (3-D) mathematicalsimulation or model of an object to be fabricated, such generationusually effected with 3-D computer-aided design (CAD) software. Themodel or simulation is mathematically separated or “sliced” into a largenumber of relatively thin, parallel, usually vertically superimposedlayers, each layer having defined boundaries and other featuresassociated with the model (and thus the actual object to be fabricated)at the level of that layer within the exterior boundaries of the object.A complete assembly or stack of all of the layers defines the entireobject, and surface resolution of the object is, in part, dependent uponthe thickness of the layers.

The mathematical simulation or model is then employed to generate anactual object by building the object, layer by superimposed layer. Awide variety of approaches to stereolithography by different companieshas resulted in techniques for fabrication of objects from both metallicand nonmetallic materials. Regardless of the material employed tofabricate an object, stereolithographic techniques usually involvedisposition of a layer of unconsolidated or unfixed materialcorresponding to each layer within the object boundaries, followed byselective consolidation or fixation of the material to at least apartially consolidated, or semi-solid, state in those areas of a givenlayer corresponding to portions of the object, the consolidated or fixedmaterial also at that time being substantially concurrently bonded to alower layer of the object being fabricated. The unconsolidated materialemployed to build an object may be supplied in particulate or liquidform, and the material itself may be consolidated or fixed, or aseparate binder material may be employed to bond material particles toone another and to those of a previously formed layer. In someinstances, thin sheets of material may be superimposed to build anobject, each sheet being fixed to a next lower sheet and unwantedportions of each sheet removed, a stack of such sheets defining thecompleted object. When particulate materials are employed, resolution ofobject surfaces is highly dependent upon particle size, whereas when aliquid is employed, surface resolution is highly dependent upon theminimum surface area of the liquid which can be fixed and the minimumthickness of a layer that can be generated. Of course, in either case,resolution and accuracy of object reproduction from the CAD file is alsodependent upon the ability of the apparatus used to fix the material toprecisely track the mathematical instructions indicating solid areas andboundaries for each layer of material. Toward that end, and dependingupon the layer being fixed, various fixation approaches have beenemployed, including particle bombardment (electron beams), disposing abinder or other fixative (such as by ink-jet printing techniques), orirradiation using heat or specific wavelength ranges.

An early application of stereolithography was to enable rapidfabrication of molds and prototypes of objects from CAD files. Thus,either male or female forms on which mold material might be disposed maybe rapidly generated. Prototypes of objects might be built to verify theaccuracy of the CAD file defining the object and to detect any designdeficiencies and possible fabrication problems before a design iscommitted to large-scale production.

In more recent years, stereolithography has been employed to develop andrefine object designs in relatively inexpensive materials, and has alsobeen used to fabricate small quantities of objects where the cost ofconventional fabrication techniques is prohibitive for same, such as inthe case of plastic objects conventionally formed by injection molding.It is also known to employ stereolithography in the custom fabricationof products generally built in small quantities or where a productdesign is rendered only once. Finally, it has been appreciated in someindustries that stereolithography provides a capability to fabricateproducts, such as those including closed interior chambers or convolutedpassageways, which cannot be fabricated satisfactorily usingconventional manufacturing techniques. It has also been recognized insome industries that a stereolithographic object or component may beformed or built around another, preexisting object or component tocreate a larger product.

However, to the inventor's knowledge, stereolithography has yet to beapplied to mass production of articles in volumes of thousands ormillions, or employed to produce, augment or enhance products includingother, preexisting components in large quantities, where minutecomponent sizes are involved, and where extremely high resolution and ahigh degree of reproducibility of results are required. In particular,the inventor is not aware of the use of stereolithography to fabricateintermediate conductive elements between semiconductor device componentsor on circuit boards. Furthermore, conventional stereolithographyapparatus and methods fail to address the difficulties of preciselylocating and orienting a number of preexisting components forstereolithographic application of material thereto without the use ofmechanical alignment techniques or to otherwise assuring precise,repeatable placement of components.

SUMMARY OF THE INVENTION

The present invention includes stereolithographically fabricatedintermediate conductive elements. Accordingly, the intermediateconductive elements of the present invention may have one or more layersof conductive material. In multilayer embodiments, the intermediateconductive elements have a plurality of superimposed, contiguous,mutually adhered layers of conductive material. Any known conductivematerial may be used to form the intermediate conductive elements of thepresent invention. Exemplary conductive materials include, withoutlimitation, electrically conductive thermoplastic elastomers and metals.

The invention also includes semiconductor device assemblies with one ormore semiconductor devices that are electrically connected to one ormore other semiconductor device components, such as carrier substrates,leads, or other semiconductor devices, by way of the intermediateconductive elements of the present invention. These intermediateconductive elements are substantially carried upon the semiconductordevice and the component to which the semiconductor device is connected.For example, when used to connect one semiconductor die to anothersemiconductor die, an intermediate conductive element of the presentinvention contacts a bond pad of the first semiconductor die, extendsacross a portion of the active surface of the first semiconductor dietowards the second semiconductor die, extends over the active surface ofthe second semiconductor die, and contacts a corresponding bond pad ofthe second semiconductor die. As another example, when the intermediateconductive elements of the present invention are used to connect asemiconductor die to a carrier substrate, one end of an intermediateconductive element may contact a contact (e.g., a bond pad) of thesemiconductor die, extend over an active surface of the semiconductordie, down a peripheral edge thereof, and over a surface of the carriersubstrate, and contact a contact pad of the carrier substrate at asecond end of the intermediate conductive element.

In another aspect, the present invention includes a printed circuitboard with a substrate that carries one or more stereolithographicallyfabricated conductive traces. Each conductive trace may have one or morelayers of conductive material. The conductive material may be, forexample, a thermoplastic conductive elastomer or a metal.

According to another aspect of the present invention, the substrate ofthe printed circuit board has two or more superimposed, contiguous,mutually adhered layers of dielectric material. One or more of theselayers of the substrate may be fabricated using stereolithographytechniques. For example, each stereolithographically formed layer of thesubstrate may be defined by, first, forming a layer of unconsolidated(i.e., uncured or particulate) dielectric material, then consolidating(i.e., curing or bonding particles) of the dielectric material inselected regions of the layer. Alternatively, each of the layers of thesubstrate may be fabricated by spraying dielectric material so as todefine the desired configuration of the layer, permitting the dielectricmaterial to at least partially harden or solidify, then using the sametechnique to form and stack one or more additional layers of dielectricmaterial to complete the substrate.

When both the intermediate conductive elements and the substrate arefabricated by stereolithographic techniques, layers of the intermediateconductive elements and of the substrate residing in the same planes canbe fabricated substantially simultaneously or sequentially.

The materials of both the intermediate conductive elements and thesubstrate may be either rigid or flexible. Accordingly, the methods ofthe present invention can be used to fabricate both rigid and flexiblecircuit boards.

The stereolithography, or “layered manufacturing,” processes that areused to fabricate the intermediate conductive elements or circuit boardsubstrates of the present invention are initiated and controlled by a3-D CAD-programmed computer.

When stereolithography is used to fabricate intermediate conductiveelements between assembled semiconductor device components, thestereolithographic method of fabricating the intermediate conductiveelements of the present invention preferably includes the use of amachine vision system to locate the assembled semiconductor devicecomponents on which intermediate conductive elements are to befabricated, as well as the various features of the semiconductor devicecomponents. The use of a machine vision system directs the alignment ofa stereolithography system with each substrate or layer for materialdisposition purposes. Accordingly, the assembled semiconductor devicecomponents need not be precisely mechanically aligned with any componentof the stereolithography system to practice the stereolithographicembodiment of the method of the present invention.

As noted previously herein, in a preferred embodiment, the intermediateconductive elements of the present invention are preferably fabricatedusing three-dimensional printing techniques, wherein a conductivematerial having the desired properties and that is solid at ambienttemperatures is heated to liquefy same. Exemplary materials that areuseful for forming intermediate conductive elements according to thepresent invention include thermoplastic conductive elastomers andmetals. The liquified conductive material is then disposed, in aprecisely focused spray (e.g., through an ink jet type nozzle) undercontrol of a computer and, preferably, responsive to input from amachine vision system, such as a pattern recognition system, to form alayer of each of the intermediate conductive elements. The conductivematerial is then permitted to at least partially harden.

A circuit board substrate may be similarly manufactured, except with adielectric material rather than a conductive material. Alternatively,other stereolithographic processes may be employed to fabricate thesubstrate. For example, the substrate may be fabricated using preciselyfocused electromagnetic radiation in the form of an ultraviolet (UV)wavelength laser to fix or cure selected regions of a layer of a liquidphotopolymer material disposed on the semiconductor device or othersubstrate.

Other features and advantages of the present invention will becomeapparent to those of skill in the art through consideration of theensuing description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a top schematic representation of a first embodiment of anassembly according to the present invention, which includes asemiconductor die with bond pads electrically connected to the contactpads of a carrier substrate by way of the intermediate conductiveelements of the present invention;

FIG. 2 is a cross-section taken along line 2-2 of FIG. 1;

FIG. 3 is a top schematic representation of a second embodiment of anassembly according to the present invention, which includes twosemiconductor dice with bond pads that are connected by way of theintermediate conductive elements of the present invention;

FIG. 4 is a cross-section taken along line 4-4 of FIG. 3;

FIG. 5 is a top schematic representation of a circuit board with asingle substrate layer, at least the intermediate conductive elements ofthe circuit board having been fabricated in accordance with the methodof the present invention;

FIG. 6 is a cross-section taken along line 6-6 of FIG. 5;

FIG. 6A is a cross-sectional representation of a variation of thecircuit board shown in FIGS. 5 and 6, in which the conductive elementsare at least partially recessed within the surrounding material;

FIG. 7 is a schematic cross-sectional representation of a multilayeredcircuit board with stereolithographically fabricated intermediateconductive elements;

FIG. 8 is a schematic representation of an assembly including a packagedsemiconductor device with leads that are electrically connected tocorresponding contact pads of a carrier substrate by way of theintermediate conductive elements of the present invention;

FIG. 9 is a schematic representation of an assembly including asemiconductor die and leads connected to the bond pads thereof by way ofthe intermediate conductive elements of the present invention;

FIG. 10 is a schematic cross-sectional representation of a semiconductordevice including a semiconductor die, intermediate conductive elementsof the present invention in communication with the bond pads of thesemiconductor die to reroute same, and a dielectric layer disposedbetween the intermediate conductive elements and the active surface ofthe semiconductor die;

FIG. 11 is a schematic representation of a first apparatus forstereolithographically fabricating structures in accordance with a firstembodiment of the method of the present invention;

FIG. 12 is a schematic representation of a second apparatus forstereolithographically fabricating structures in accordance with asecond embodiment of the method of the present invention; and

FIG. 13 is partial cross-sectional schematic representation of asemiconductor device disposed on a platform of a stereolithographicapparatus for the formation of intermediate conductive elements betweencontacts of the assembled semiconductor device components.

DETAILED DESCRIPTION OF THE INVENTION Stereolithography Apparatus andMethods

FIG. 11 schematically depicts various components, and operation, ofexemplary stereolithography apparatus 80 to facilitate the reader'sunderstanding of the technology employed in implementation of themethods of the present invention, although those of ordinary skill inthe art will understand and appreciate that apparatus of other designsand manufacture may be employed in practicing the method of the presentinvention. Apparatus 80 and the operation thereof are described in greatdetail in United States Patents assigned to 3D Systems, Inc. ofValencia, Calif., such patents including, without limitation, U.S. Pat.Nos. 4,575,330; 4,929,402; 4,996,010; 4,999,143; 5,015,424; 5,058,988;5,059,021; 5,059,359; 5,071,337; 5,076,974; 5,096,530; 5,104,592;5,123,734; 5,130,064; 5,133,987; 5,143,663; 5,164,128; 5,174,931;5,174,943; 5,182,055; 5,182,056; 5,182,715; 5,184,307; 5,192,469;5,192,559; 5,209,878; 5,234,636; 5,236,637; 5,238,639; 5,248,456;5,256,340; 5,258,146; 5,267,013; 5,273,691; 5,321,622; 5,345,391;5,358,673; 5,447,822; 5,481,470; 5,495,328; 5,554,336; 5,556,590;5,569,431; 5,571,471; 5,573,722; 5,609,812; 5,609,813; 5,610,824;5,630,981; 5,637,169; 5,651,934; 5,667,820; 5,676,904; 5,688,464;5,693,144; 5,711,911; 5,779,967; 5,814,265; 5,850,239; 5,854,748;5,855,718; 5,885,511; 5,897,825; 5,902,537; 5,902,538; 5,904,889;5,943,235; and 5,945,058. The disclosure of each of the foregoingpatents is hereby incorporated herein by this reference.

With continued reference to FIG. 11 and as noted above, a 3-D CADdrawing of an object to be fabricated in the form of a data file isplaced in the memory of a computer 82 controlling the operation ofapparatus 80 if computer 82 is not a CAD computer in which the originalobject design is effected. In other words, an object design may beeffected in a first computer in an engineering or research facility andthe data files transferred via wide or local area network, tape, disc,CD-ROM, or as otherwise known in the art to computer 82 of apparatus 80for object fabrication.

The data is preferably formatted in an STL (for STereoLithography) file,STL being a standardized format employed by a majority of manufacturersof stereolithography equipment. Fortunately, the format has been adoptedfor use in many solid-modeling CAD programs, so translation from anotherinternal geometric database format is often unnecessary. In an STL file,the boundary surfaces of an object are defined as a mesh ofinterconnected triangles.

Apparatus 80 also includes a reservoir 84 (which may comprise aremovable reservoir interchangeable with others containing differentmaterials) of an unconsolidated material 86 to be employed infabricating the intended object. Unconsolidated material 86 useful inapparatus 80 is a liquid, photo-curable polymer, or “photopolymer” thatcures in response to light in the UV wavelength range. The surface level88 of material 86 is automatically maintained at an extremely precise,constant magnitude by devices known in the art responsive to output ofsensors within apparatus 80 and preferably under control of computer 82.A support platform or elevator 90, precisely vertically movable in fine,repeatable increments responsive to control of computer 82, is locatedfor movement downward into and upward out of material 86 in reservoir84.

An object may be fabricated directly on platform 90, or on a substratedisposed on platform 90. When the object is to be fabricated on asubstrate disposed on platform 90, the substrate may be positioned onplatform 90 and secured thereto by way of one or more base supports 122(FIG. 13). Such base supports 122 may be fabricated before orsimultaneously with the stereolithographic fabrication of one or moreobjects on platform 90 or a substrate disposed thereon. These basesupports 122 may support, or prevent lateral movement of, the substraterelative to a surface 100 of platform 90. Base supports 122 may alsoprovide a perfectly horizontal reference plane for fabrication of one ormore objects thereon, as well as facilitate the removal of a substratefrom platform 90 following the stereolithographic fabrication of one ormore objects on the substrate. Moreover, where a so-called “recoater”blade 102 is employed to form a layer of material on platform 90 or asubstrate disposed thereon, base supports 122 can preclude inadvertentcontact of recoater blade 102, to be described in greater detail below,with surface 100 of platform 90.

Apparatus 80 has a UV wavelength range laser plus associated optics andgalvanometers (collectively identified as laser 92) for controlling thescan of laser beam 96 in the X-Y plane across platform 90. Laser 92 hasassociated therewith a mirror 94 to reflect laser beam 96 downwardly aslaser beam 98 toward surface 100 of platform 90. Laser beam 98 istraversed in a selected pattern in the X-Y plane, that is to say in aplane parallel to surface 100, by initiation of the galvanometers undercontrol of computer 82 to at least partially cure, by impingementthereon, selected portions of material 86 disposed over surface 100 toat least a partially consolidated (e.g., semisolid) state. The use ofmirror 94 lengthens the path of the laser beam, effectively doublingsame, and provides a more vertical laser beam 98 than would be possibleif the laser 92 itself were mounted directly above platform surface 100,thus enhancing resolution.

Referring now to FIGS. 11 and 13, data from the STL files resident incomputer 82 is manipulated to build an object, such as an intermediateconductive element 20, 20′, 20″, or 20′″, illustrated in FIGS. 1-10, orbase supports 122, one layer at a time. Accordingly, the datamathematically representing one or more of the objects to be fabricatedare divided into subsets, each subset representing a slice or layer ofthe object. The division of data is effected by mathematicallysectioning the 3-D CAD model into at least one layer, a single layer ora “stack” of such layers representing the object. Each slice may be fromabout 0.0001 to about 0.0300 inch thick. As mentioned previously, athinner slice promotes higher resolution by enabling better reproductionof fine vertical surface features of the object or objects to befabricated.

When one or more base supports 122 are to be stereolithographicallyfabricated, base supports 122 may be programmed as a separate STL filefrom the other objects to be fabricated. The primary STL file for theobject or objects to be fabricated and the STL file for base support(s)122 are merged.

Before fabrication of a first layer for a support 122 or an object to befabricated is commenced, the operational parameters for apparatus 80 areset to adjust the size (diameter if circular) of the laser light beamused to cure material 86. In addition, computer 82 automatically checksand, if necessary, adjusts by means known in the art the surface level88 of material 86 in reservoir 84 to maintain same at an appropriatefocal length for laser beam 98. U.S. Pat. No. 5,174,931, referencedabove and previously incorporated herein by reference, discloses onesuitable level control system. Alternatively, the height of mirror 94may be adjusted responsive to a detected surface level 88 to cause thefocal point of laser beam 98 to be located precisely at the surfacelevel 88 of material 86 if the surface level 88 is permitted to vary,although this approach is more complex. Platform 90 may then besubmerged in material 86 in reservoir 84 to a depth equal to thethickness of one layer or slice of the object to be formed, and theliquid surface level 88 is readjusted as required to accommodatematerial 86 displaced by submergence of platform 90. Laser 92 is thenactivated so laser beam 98 will scan unconsolidated (e.g., liquid orpowdered) material 86 disposed over surface 100 of platform 90 to atleast partially consolidate (e.g., polymerize to at least a semisolidstate) material 86 at selected locations, defining the boundaries of afirst layer 122A of base support 122 and filling in solid portionsthereof. Platform 90 is then lowered by a distance equal to thethickness of second layer 122B, and laser beam 98 scanned over selectedregions of the surface of material 86 to define and fill in the secondlayer while simultaneously bonding the second layer to the first. Theprocess may be repeated as often as necessary, layer by layer, untilbase support 122 is completed. Platform 90 is then moved relative tomirror 94 to form any additional base supports 122 on platform 90 or asubstrate disposed thereon or to fabricate objects upon platform 90,base support 122, or a substrate, as provided in the control software.The number of layers required to erect support 122 or one or more otherobjects to be formed depends upon the height of the object or objects tobe formed and the desired layer thicknesses of layers 20A, 20B, etc. Thelayers of a stereolithographically fabricated structure may havedifferent thicknesses.

If a recoater blade 102 is employed, the process sequence is somewhatdifferent. In this instance, surface 100 of platform 90 is lowered intounconsolidated (e.g., liquid) material 86 below surface level 88 adistance greater than a thickness of a single layer of material 86 to becured, then raised above surface level 88 until platform 90, a substratedisposed thereon, or a structure being formed on platform 90 or asubstrate thereon is precisely one layer's thickness below blade 102.Blade 102 then sweeps horizontally over platform 90 or (to save time) atleast over a portion thereof on which one or more objects are to befabricated to remove excess material 86 and leave a film of preciselythe desired thickness. Platform 90 is then lowered so that the surfaceof the film and surface level 88 are coplanar and the surface of theunconsolidated material 86 is still. Laser 92 is then initiated to scanwith laser beam 98 and define the first layer 20A. The process isrepeated, layer by layer, to define each succeeding layer andsimultaneously bond same to the next lower layer until all of the layersof the object or objects to be fabricated are completed. A more detaileddiscussion of this sequence and apparatus for performing same isdisclosed in U.S. Pat. No. 5,174,931, previously incorporated herein byreference.

As an alternative to the above approach to preparing a layer of material86 for scanning with laser beam 98, a layer of unconsolidated (e.g.,liquid) material 86 may be formed on surface 100 of support platform 90,on a substrate disposed on platform 90, or on one or more objects beingfabricated by lowering platform 90 to flood material 86 over surface100, over a substrate disposed thereon, or over the highest completedlayer of the object or objects being formed, then raising platform 90and horizontally traversing a so-called “meniscus” blade horizontallyover platform 90 to form a layer of unconsolidated material having thedesired thickness over platform 90, the substrate, or each of theobjects being formed. Laser 92 is then initiated and a laser beam 98scanned over the layer of unconsolidated material to define at least theboundaries of the solid regions of the next higher layer of the objector objects being fabricated.

Yet another alternative to layer preparation of unconsolidated (e.g.,liquid) material 86 is to merely lower platform 90 to a depth equal tothat of a layer of material 86 to be scanned, and to then traverse acombination flood bar and meniscus bar assembly horizontally overplatform 90, a substrate disposed on platform 90, or one or more objectsbeing formed to substantially concurrently flood material 86 thereoverand to define a precise layer thickness of material 86 for scanning.

All of the foregoing approaches to liquid material flooding and layerdefinition and apparatus for initiation thereof are known in the art andare not material to practice of the present invention, so no furtherdetails relating thereto will be provided herein.

In practicing the present invention, a commercially availablestereolithography apparatus operating generally in the manner as thatdescribed above with respect to apparatus 80 of FIG. 11 may be employed,but with further additions and modifications as hereinafter describedfor practicing the method of the present invention. For example and notby way of limitation, the SLA-250/50HR, SLA-5000 and SLA-7000stereolithography systems, each offered by 3D Systems, Inc., ofValencia, Calif., are suitable for modification. Photopolymers believedto be suitable for use in practicing the present invention includeCibatool SL 5170 and SL 5210 resins for the SLA-250/50HR system,Cibatool SL 5530 resin for the SLA-5000 and 7000 systems, and CibatoolSL 7510 resin for the SLA-7000 system. All of these photopolymers areavailable from Ciba Specialty Chemicals Inc.

By way of example and not limitation, the layer thickness of material 86to be formed, for purposes of the invention, may be on the order ofabout 0.0001 to 0.0300 inch, with a high degree of uniformity. It shouldbe noted that different material layers may have different heights, soas to form a structure of a precise, intended total height or to providedifferent material thicknesses for different portions of the structure.The size of the laser beam “spot” impinging on the surface of material86 to cure same may be on the order of 0.001 inch to 0.008 inch.Resolution is preferably ±0.0003 inch in the X-Y plane (parallel tosurface 100) over at least a 0.5 inch×0.25 inch field from a centerpoint, permitting a high resolution scan effectively across a 1.0inch×0.5 inch area. Of course, it is desirable to have substantiallythis high a resolution across the entirety of surface 100 of platform 90to be scanned by laser beam 98, such area being termed the “field ofexposure,” such area being substantially coextensive with the visionfield of a machine vision system employed in the apparatus of theinvention as explained in more detail below. The longer and moreeffectively vertical the path of laser beam 96/98, the greater theachievable resolution.

Another apparatus 180 useful in implementing the methods of the presentinvention, referred to as a thermal stereolithography apparatus, isschematically illustrated in FIG. 12. Apparatus 180 and the operation ofapparatus 180 are described in great detail in United States Patentsassigned to 3D Systems, Inc. of Valencia, Calif., such patentsincluding, without limitation, U.S. Pat. Nos. 5,141,680; 5,344,298;5,501,824; 5,569,349; 5,672,312; 5,695,707; 5,776,409; 5,855,836. Thedisclosure of each of the foregoing patents is hereby incorporatedherein by this reference.

As noted above, a 3-D CAD drawing of an object to be fabricated in theform of a data file may be placed in the memory of a computer 182controlling the operation of apparatus 180 if computer 182 is not a CADcomputer in which the original object design is effected. Preferably,the data is formatted in an STL file.

Apparatus 180 includes a support platform or elevator 190, preciselyvertically movable in fine, repeatable increments responsive to controlof computer 182. An object may be fabricated directly on platform 190,or on a substrate disposed on platform 190. When the object is to befabricated on a substrate disposed on platform 190, the substrate may bepositioned on platform 190 and secured thereto by way of one or morebase supports (see FIG. 13). Such base supports 122 may be fabricatedbefore or simultaneously with the stereolithographic fabrication of oneor more objects on platform 190 or a substrate disposed thereon. Thesebase supports 122 may support, or prevent lateral movement of, thesubstrate relative to a surface 200 of platform 190. Base supports 122may also provide a perfectly horizontal reference plane for fabricationof one or more objects thereon, as well as facilitate the removal of asubstrate from platform 190 following the stereolithographic fabricationof one or more objects on the substrate.

Apparatus 180 also includes a reservoir 184 (which may comprise aremovable reservoir interchangeable with others containing differentmaterials) of an unconsolidated material 186 to be employed infabricating the intended object. Unconsolidated material 186 useful withapparatus 180 is a heated, flowable material that is typically solid atthe operating temperatures of a semiconductor device.

One or more spray heads 192 of apparatus 180 communicate with andreceive unconsolidated material 186 from reservoir 184. Each spray head192, under control of computer 182, effects the deposition ofunconsolidated material 186 in the X-Y plane of platform 190, on asubstrate disposed on platform 190, or on an object being formed.

Data from the STL files resident in computer 182 is manipulated to buildan object, such as intermediate conductive element 20, illustrated inFIGS. 1-10, or base supports 122, illustrated in FIG. 13, one layer at atime. Accordingly, the data mathematically representing one or more ofthe objects to be fabricated are divided into subsets, each subsetrepresenting a slice or layer of the object. The division of data iseffected by mathematically sectioning the 3-D CAD model into at leastone layer, a single layer or a “stack” of such layers representing theobject. Each slice may be from about 0.003 to about 0.030 inch thick. Asmentioned previously, a thinner slice promotes higher resolution byenabling better reproduction of fine vertical surface features of theobject or objects to be fabricated.

When one or more base supports 122 are to be stereolithographicallyfabricated, base supports 122 may be programmed as an STL file separatefrom the STL files for other objects to be fabricated. The primary STLfile for the object or objects to be fabricated and the STL file forbase support(s) 122 are merged.

Before fabrication of a first layer for a support 122 or an object to befabricated is commenced, the operational parameters for apparatus 180are set to adjust the size (diameter if circular) of the stream ofunconsolidated material 186 to be ejected from each spray head 192. Inaddition, computer 182 automatically checks and, if necessary, adjustsby means known in the art the surface level 188 of platform 190 tomaintain same at an appropriate length from spray heads 192 to obtain anobject having the desired resolution. U.S. Pat. No. 5,174,931,referenced above and previously incorporated herein by reference,discloses one suitable level control system.

Each spray head 192 is then activated so as to deposit unconsolidatedmaterial 186 over surface 200 of platform 190 to form at least theboundaries of a first layer 122A of base support 122 (FIG. 13) and tofill in solid portions thereof. The deposited material 186 is thenpermitted to at least partially harden, or consolidate, prior to forminganother layer thereon. Each layer of the object being fabricated may belaterally supported by a material that remains substantiallyunconsolidated at ambient temperatures and that, preferably, will notadhere to the just-formed layer of material 186.

After a layer is formed, platform 190 may be lowered a distancesubstantially equal to the thickness of the just-formed layer so as tomaintain a substantially constant distance between spray heads 192 andthe surface on which the next layer of unconsolidated material 186 is tobe disposed. Spray heads 192 may then be scanned over selected regionsof surface 200 or the surface of the previously formed layer to defineand fill in the second layer while simultaneously bonding the secondlayer to the first. The process may be then repeated, as often asnecessary, layer by layer, until base support 122 is completed. Thenumber of layers required to erect support 122 or one or more otherobjects to be formed depends upon the height of the object or objects tobe formed and the desired thicknesses of layers 20A, 20B, etc. Thelayers of a stereolithographically fabricated structure may havedifferent thicknesses.

Exemplary commercially available thermal stereolithography apparatusoperating generally in the manner as that described above with respectto apparatus 180 of FIG. 12 include, but are not limited to, theTHERMOJET™ printer offered by 3D Systems, Inc., of Valencia, Calif. Ofcourse, as with apparatus 80 depicted in FIG. 11, apparatus 180 may beemployed with further additions and modifications as hereinafterdescribed. Thermoplastic materials, or “thermopolymers,” believed to besuitable for use in practicing the method of the present invention incombination with apparatus 180 include ThermoJet 88 Thermopolymer,available from 3D Systems, Inc., as well as other nonconductive andelectrically conductive thermopolymers known in the art.

By way of example and not limitation, the layer thickness of material186 to be formed, for purposes of the invention, may be on the order ofabout 0.003 to 0.030 inch, with a high degree of uniformity. It shouldbe noted that different material layers may have different heights, soas to form a structure of a precise, intended total height or to providedifferent material thicknesses for different portions of the structure.Resolution is preferably about 300 dpi (dots per inch) or about 0.003inch in the X-Y plane (parallel to surface 200). Of course, it isdesirable to have substantially this high a resolution across the entiresurface 200 of platform 190 to be scanned by spray heads 192, such areabeing termed the “field of exposure,” such area being substantiallycoextensive with the vision field of a machine vision system employed inthe apparatus of the invention as explained in more detail below. Ofcourse, since apparatus 180 deposits material by way of one or morespray heads 192, the resolution with which an object can be formed byapparatus 180 is dependent, at least in part, upon spray heads 192 andthe type of material 186 deposited thereby.

Referring now to both FIGS. 11 and 12, it should be noted that apparatus80, 180 useful in the methods of the present invention include cameras140 which are in communication with computers 82, 182, respectively, andare preferably located, as shown, in close proximity to optics andmirror 94 located above surface 100, 200 of support platform 90, 190.Each camera 140 may be any one of a number of commercially availablecameras, such as capacitive-coupled discharge (CCD) cameras availablefrom a number of vendors. Suitable circuitry as required for adaptingthe output of camera 140 for use by computer 82, 182 may be incorporatedin a board 142 installed in computer 82, 182 which is programmed asknown in the art to respond to images generated by camera 140 andprocessed by board 142. Camera 140 and board 142 may together comprise aso-called “machine vision system” and, specifically, a “patternrecognition system” (PRS), the operation of which will be describedbriefly below for a better understanding of the present invention.Alternatively, a self-contained machine vision system available from acommercial vendor of such equipment may be employed. For example, andwithout limitation, such systems are available from Cognex Corporationof Natick, Mass. For example, the apparatus of the Cognex BGA InspectionPackage™ or the SMD Placement Guidance Package™ may be adapted to thepresent invention, although it is believed that the MVS-8000™ productfamily and the Checkpoint® product line, the latter employed incombination with Cognex PatMax™ software, may be especially suitable foruse in the present invention.

It is noted that a variety of machine vision systems are in existence,examples of which and their various structures and uses are described,without limitation, in U.S. Pat. Nos. 4,526,646; 4,543,659; 4,736,437;4,899,921; 5,059,559; 5,113,565; 5,145,099; 5,238,174; 5,463,227;5,288,698; 5,471,310; 5,506,684; 5,516,023; 5,516,026; and 5,644,245.The disclosure of each of the immediately foregoing patents is herebyincorporated by this reference.

Stereolithographic Fabrication of the Conductive Elements

In order to facilitate fabrication of one or more intermediateconductive elements 20 in accordance with the method of the presentinvention with apparatus 80, 180, a data file representative of thesize, configuration, thickness and surface topography of, for example, aparticular type and design of semiconductor device 10 or other substrateupon which one or more intermediate conductive elements 20 are to befabricated is placed in the memory of computer 82, 182.

One or more semiconductor devices 10, carrier substrates 30, or othersemiconductor device components may be placed on surface 100, 200 ofplatform 90, 190 for fabrication of intermediate conductive elements 20in communication with contact pads thereof (e.g., bond pads 12 ofsemiconductor device 10, shown in FIGS. 1-4). One or more semiconductordevices 10, carrier substrates 30, or other semiconductor devicecomponents may be held on or supported above platform 90, 190 bystereolithographically formed base supports 122. When apparatus 80 isused, these base supports 122 are formed by sequentially disposing oneor more layers of material 86 on surface 100 and selectively alteringmaterial 86 by use of laser 92. Apparatus 180 forms base supports 122 byselectively depositing one or more layers of material 186 from sprayheads 192.

Camera 140 is then activated to locate the position and orientation ofeach semiconductor device 10, carrier substrate 30, or other type ofsemiconductor device component upon which intermediate conductiveelements 20 are to be fabricated. The features of each semiconductordevice 10, carrier substrate 30, or other type of semiconductor devicecomponent are compared with those in the data file residing in memory,the locational and orientational data for each semiconductor device 10,carrier substrate 30, or other type of semiconductor device componentthen also being stored in memory. It should be noted that the data filerepresenting the design size, shape and topography for eachsemiconductor device 10, carrier substrate 30, or other type ofsemiconductor device component may be used at this juncture to detectphysically defective or damaged semiconductor devices 10, carriersubstrates 30, or other types of semiconductor device components priorto fabricating intermediate conductive elements 20 thereon or beforeconducting further packaging of semiconductor devices 10, carriersubstrates 30, or other types of semiconductor device components.Accordingly, such damaged or defective semiconductor devices 10, carriersubstrates 30, or other types of semiconductor device components can bedeleted from the process of fabricating intermediate conductive elements20 and from further packaging. It should also be noted that data filesfor more than one type (size, thickness, configuration, surfacetopography) of each semiconductor device 10, carrier substrate 30, orother type of semiconductor device component may be placed in computermemory and computer 82, 182 programmed to recognize not only thelocations and orientations of each semiconductor device 10, carriersubstrate 30, or other type of semiconductor device component, but alsothe type of semiconductor component at each location upon platform 90,190 so that material 86 may be at least partially consolidated by laserbeam 98 or material 186 selectively deposited by spray heads 192 in thecorrect pattern and to the height required to define intermediateconductive elements 20 in the appropriate, desired locations on eachsemiconductor device 10, carrier substrate 30, or other semiconductordevice component.

Fabrication of the Conductive Elements by Photo-Stereolithography

When apparatus 80 is used, as depicted in FIGS. 11 and 13, the one ormore semiconductor devices 10, carrier substrates 30, or othersemiconductor device components on platform 90 may then be submergedpartially below the surface level 88 of unconsolidated (e.g., liquid)material 86 to a depth greater than the thickness of a first layer ofmaterial 86 to be at least partially consolidated (e.g., cured to atleast a semisolid state) to form the lowest layer of each intermediateconductive element 20 at the appropriate location or locations on eachsemiconductor device 10, carrier substrate 30, or other type ofsemiconductor device component, then raised to a depth equal to thelayer thickness, the surface level 88 of material 86 being allowed tobecome calm. Photopolymers that are useful as material 86 exhibit adesirable dielectric constant and low shrinkage upon cure, are ofsufficient (i.e., semiconductor grade) purity, exhibit good adherence toother semiconductor device materials, and have a coefficient of thermalexpansion (CTE) similar to that of the materials adjacent thereto.Preferably, the CTE of material 86 is sufficiently similar to that ofthe adjacent materials to prevent undue stressing thereof during thermalcycling of semiconductor device 10, carrier substrate 30, or othersemiconductor device component in testing, subsequent processing, andsubsequent normal operation. Exemplary photopolymers exhibiting theseproperties are believed to include, but are not limited to, theabove-referenced resins from Ciba Specialty Chemicals Inc. One area ofparticular concern in determining resin suitability is the substantialabsence of mobile ions and, specifically, fluorides.

Laser 92 is then activated and scanned to direct laser beam 98, undercontrol of computer 82, toward specific locations of surface level 88relative to each semiconductor device 10, carrier substrate 30, or othertype of semiconductor device component to effect the aforementionedpartial cure of material 86 to form a first layer 20A of eachintermediate conductive element 20. Platform 90 is then lowered intoreservoir 84 and raised a distance equal to the desired thickness ofanother layer 20B of each intermediate conductive element 20, and laser92 is activated to add another layer 20B to each intermediate conductiveelement 20 under construction. This sequence continues, layer by layer,until each of the layers of intermediate conductive elements 20 has beencompleted.

In FIG. 13, the first layer of intermediate conductive element 20 isidentified by numeral 20A, and the second layer is identified by numeral20B. Likewise, the first layer of base support 122 is identified bynumeral 122A and the second layer thereof is identified by numeral 122B.As illustrated, base support 122 and intermediate conductive element 20have only two layers. Intermediate conductive elements 20 with anynumber of layers are, however, within the scope of the presentinvention.

In addition to being useful for fabricating intermediate conductiveelements 20, apparatus 80 may also be used to fabricate nonconductivestructures, such as dielectric layers and substrate layers, such as thenonconductive support layers of a circuit board or other carriersubstrate.

When apparatus 80 is employed to fabricate one or more intermediateconductive elements 20 or other structures (e.g., one or more layers ofa carrier substrate 30), each layer 20A, 20B of each intermediateconductive element 20 is preferably built by first defining any internaland external object boundaries of that layer with laser beam 98, thenhatching solid areas of intermediate conductive elements 20 locatedwithin the object boundaries with laser beam 98. An internal boundary ofa layer may comprise an aperture, a through hole, a void, or a recess incarrier substrate 30, for example. If a particular layer includes aboundary of a void in the object above or below that layer, then laserbeam 98 is scanned in a series of closely spaced, parallel vectors so asto develop a continuous surface, or skin, with improved strength andresolution. The time it takes to form each layer depends upon thegeometry thereof, the surface tension and viscosity of material 86, andthe thickness of that layer.

Alternatively, intermediate conductive elements 20 or otherstereolithographically fabricated structures may each be formed as apartially cured outer skin extending above active surface 14 ofsemiconductor device 10 or above surface 34 of carrier substrate 30 andforming a dam within which unconsolidated material 86 can be contained.This may be particularly useful where intermediate conductive elements20 or other structures protrude a relatively high distance above activesurface 14. In this instance, support platform 90 may be submerged sothat material 86 enters the area within the dam and raised above surfacelevel 88, and then laser beam 98 activated and scanned to at leastpartially cure material 86 residing within the dam or, alternatively, tomerely cure a “skin,” a final cure of the material of intermediateconductive elements 20 or other structures under construction beingeffected subsequently by broad-source UV radiation in a chamber, or bythermal cure in an oven. In this manner, intermediate conductiveelements 20 and other structures of extremely precise dimensions may beformed of material 86 by apparatus 80 in minimal time.

Once intermediate conductive elements 20 or other structures, or atleast the outer skins thereof, have been fabricated, platform 90 iselevated above surface level 88 of material 86 and platform 90 isremoved from apparatus 80, along with semiconductor device 10, carriersubstrate 30, or another semiconductor device component upon whichintermediate conductive elements 20 or other structures have beenstereolithographically fabricated. Excess, unconsolidated material 86(e.g., excess uncured liquid) may be manually removed from platform 90,from any substrate disposed thereon, and from intermediate conductiveelements 20 or other stereolithographically fabricated structures. Eachsemiconductor device 10, carrier substrate 30, or other semiconductordevice component is removed from platform 90, such as by cutting thesemiconductor device component free of base supports 122. Alternatively,base supports 122 may be configured to readily release semiconductordevices 10, carrier substrates 30, or other semiconductor devicecomponents. As another alternative, a solvent may be employed to releasebase supports 122 from platform 90. Such release and solvent materialsare known in the art. See, for example, U.S. Pat. No. 5,447,822referenced above and previously incorporated herein by reference.

The stereolithographically fabricated intermediate conductive elements20 or other structures, as well as semiconductor device 10, carriersubstrate 30, or another semiconductor device component upon which thesestructures have been fabricated, may also be cleaned by use of knownsolvents that will not substantially degrade, deform, or damage thestereolithographically fabricated structures, such as intermediateconductive elements 20, or the semiconductor device components.

As noted previously, intermediate conductive elements 20 or otherstereolithographically fabricated structures may then requirepostcuring. Intermediate conductive elements 20 or other structures mayhave regions of unconsolidated material contained within a boundary orskin thereof, or material 86 may be only partially consolidated (e.g.,polymerized or cured) and exhibit only a portion (typically 40% to 60%)of its fully consolidated strength. Postcuring to completely hardenintermediate conductive elements 20 or other stereolithographicallyfabricated structures may be effected in another apparatus projecting UVradiation in a continuous manner over the stereolithographicallyfabricated structures or by thermal completion of the initial,UV-initiated partial cure.

Fabrication of the Conductive Elements by Thermal Stereolithography

Referring again to FIGS. 12 and 13, when apparatus 180 is used tofabricate intermediate conductive elements 20, spray heads 192 directliquified material 186 onto the appropriate location or locations of theone or more semiconductor devices 10, carrier substrates 30, or othersemiconductor device components on platform 190, 90. The material ispermitted to solidify to form the lowest layer 20A of each intermediateconductive element 20. Thermoplastic polymers that are useful asmaterial 186 exhibit desirable electrical conductivity, exhibit lowshrinkage upon solidification, substantially maintain their structuralintegrity under normal operating conditions (e.g., operatingtemperatures of the semiconductor device), are of sufficient (i.e.,semiconductor grade) purity, exhibit good adherence to othersemiconductor device materials, and have a coefficient of thermalexpansion (CTE) similar to that of the materials adjacent thereto.Preferably, the CTE of material 186 is sufficiently similar to that ofthe adjacent materials to prevent undue stressing thereof during thermalcycling of semiconductor device 10, carrier substrate 30, or anothersemiconductor device component in testing, subsequent processing, andsubsequent normal operation.

Platform 190 is then lowered a distance substantially equal to the nextlayer 20B of each intermediate conductive element 20 under construction.Heated conductive material 186 is then disposed by spray heads 192 ontoappropriate locations of the previously fabricated layer 20A of eachintermediate conductive element 20 to form layer 20B. This sequencecontinues, layer by layer, until each of the layers of intermediateconductive elements 20 have been completed.

In addition to being useful for fabricating intermediate conductiveelements 20, apparatus 180 may also be used to fabricate nonconductivestructures, such as dielectric layers and substrate layers, such as thenonconductive support layers of a circuit board or other carriersubstrate.

Once intermediate conductive elements 20 or other structures have beenfabricated, platform 190 is removed from apparatus 180, along withsemiconductor device 10, carrier substrate 30, or another semiconductordevice component upon which intermediate conductive elements 20 or otherstructures have been stereolithographically fabricated. Eachsemiconductor device 10, carrier substrate 30, or other semiconductordevice component is removed from platform 190, such as by cutting thesemiconductor device component free of base supports 122. Alternatively,base supports 122 may be configured to readily release semiconductordevices 10, carrier substrates 30, or other semiconductor devicecomponents. As another alternative, a solvent may be employed to releasebase supports 122 from platform 190. Such release and solvent materialsare known in the art. See, for example, U.S. Pat. No. 5,447,822referenced above and previously incorporated herein by reference.

The stereolithographically fabricated intermediate conductive elements20 or other structures, as well as semiconductor device 10, carriersubstrate 30, or another semiconductor device component upon which thesestructures have been fabricated, may also be cleaned by use of knownsolvents that will not substantially degrade, deform, or damage thestereolithographically fabricated structures, such as intermediateconductive elements 20, or the semiconductor device components.

The use of a stereolithographic process as exemplified above tofabricate intermediate conductive elements 20 is particularlyadvantageous since a large number of intermediate conductive elements 20may be substantially simultaneously fabricated in a short time, thepositioning thereof is computer controlled and extremely precise,wastage of material is minimal, and the stereolithography methodrequires minimal handling of semiconductor devices 10, carriersubstrates 30, or other semiconductor device components.

Stereolithography is also an advantageous method of fabricatingintermediate conductive elements 20 according to the present inventionsince stereolithography can be conducted at temperatures that will notdamage or induce significant thermal stress on the semiconductor devicecomponents during fabrication of intermediate conductive elements 20thereon. The stereolithography fabrication process may also be used tosimultaneously form intermediate conductive elements 20 on severalsemiconductor device components or assemblies, saving fabrication timeand expense. As the stereolithography method of the present inventionrecognizes specific semiconductor devices 10, carrier substrates 30, andother semiconductor device components, variations between differentsemiconductor device components are accommodated. Accordingly, when thestereolithography method of the present invention is employed,intermediate conductive elements 20 can be simultaneously fabricated ondifferent types of semiconductor device components or assemblies ofsemiconductor device components.

Semiconductor Device Components and Assemblies Including the ConductiveElements

Referring now to FIGS. 1 and 2, an assembly 1 of a semiconductor device10 and a carrier substrate 30 is illustrated. Semiconductor device 10 isa semiconductor die that includes bond pads 12, which are also referredto herein as contact pads or contacts for simplicity, on an activesurface 14 thereof. A back side 16 of semiconductor device 10 isdisposed against a surface 34 of carrier substrate 30. Bond pads 12 ofsemiconductor device 10 are electrically connected to correspondingcontact pads 32 of carrier substrate 30 by way of intermediateconductive elements 20. For simplicity, contact pads 32 are alsoreferred to herein as contacts.

Intermediate conductive elements 20, which are fabricated bystereolithographic techniques, are formed from a conductive material,such as a conductive elastomer or a metal. Intermediate conductiveelements 20 may each include a single layer or a plurality ofsuperimposed, contiguous, mutually adhered layers of conductivematerial.

Each intermediate conductive element 20 is substantially entirelycarried along the length thereof upon either semiconductor device 10 orcarrier substrate 30. As illustrated in FIG. 2, each intermediateconductive element 20 extends across a portion of active surface 14 ofsemiconductor device 10, down a lateral edge 18 of semiconductor device10, and across a portion of surface 34 of carrier substrate 30. A firstend 22 of each intermediate conductive element 20 is in contact with abond pad 12 and a second end 24 of intermediate conductive element 20 isconnected to a contact pad 32 of carrier substrate 30.

FIGS. 3 and 4 illustrate another exemplary assembly 2 with intermediateconductive elements 20 of the present invention. Assembly 2 includes twosemiconductor devices 10, 10′ disposed on a carrier substrate 30. Asillustrated, each semiconductor device 10, 10′ is a semiconductor diethat includes bond pads 12, 12′, or contact pads or contacts, on anactive surface 14, 14′ thereof. Back sides 16, 16′ of semiconductordevices 10, 10′ are disposed over a surface 34 of carrier substrate 30,with a lateral edge 18 of one semiconductor device 10 abutting a lateraledge 18′ of the other semiconductor device 10′. Corresponding bond pads12, 12′ of the two semiconductor devices 10, 10′ are electricallyconnected to each other by way of intermediate conductive elements 20.

As in assembly 1 depicted in FIGS. 1 and 2, intermediate conductiveelements 20 of assembly 2 are stereolithographically fabricated from anelectrically conductive material, such as an electrically conductivethermoplastic polymer or a metal. Since intermediate conductive elements20 are stereolithographically fabricated, each intermediate conductiveelement 20 may include one layer or a plurality of superimposed,contiguous, mutually adhered layers of conductive material.

With continued reference to FIGS. 3 and 4, substantially the entirelengths of intermediate conductive elements 20 are carried bysemiconductor devices 10, 10′. As illustrated in FIG. 4, eachintermediate conductive element 20 extends across a portion of activesurface 14 of a first semiconductor device 10, over an interface 17between abutting lateral edges 18, 18′ of the two semiconductor devices10, 10′, and across a portion of active surface 14′ of the secondsemiconductor device 10′. A first end 22 of each intermediate conductiveelement 20 is in contact with a bond pad 12 of one semiconductor device10 and a second end 24 of intermediate conductive element 20 isconnected to a bond pad 12′ of the other semiconductor device 10′ (FIG.3).

Turning now to FIGS. 5 and 6, an embodiment of a carrier substrate 30,in this case a circuit board, is schematically depicted that includesstereolithographically fabricated intermediate conductive elements 20′according to the present invention. Carrier substrate 30 includes asingle substrate layer 31, intermediate conductive elements 20′ carriedby carrier substrate 30, and a contact pad 32, or contact, at an end ofeach intermediate conductive element 20′. Intermediate conductiveelements 20′ that traverse more than one plane of carrier substrate 30include vertically extending vias 36 along the lengths thereof. Vias 36are located in through holes 38 formed through substrate layer 31.

As discussed previously herein, intermediate conductive elements 20′ maybe fabricated by stereolithographic techniques. Contact pads 32 may alsobe stereolithographically fabricated. Accordingly, each intermediateconductive element 20′ and contact pad 32 may include one layer or aplurality of superimposed, contiguous, mutually adhered layers ofconductive material. Exemplary conductive materials that may be used toform intermediate conductive elements 20′ and contact pads 32 includeknown thermoplastic conductive polymers and metals. In order tofabricate intermediate conductive elements 20′ on both sides ofsubstrate layer 31, a first set of intermediate conductive elements 20′is fabricated on a first side of substrate layer 31. Substrate layer 31is then inverted and a second set of intermediate conductive elements20′ is fabricated on a second side of substrate layer 31.

Substrate layer 31 may similarly be fabricated from dielectric materialsby stereolithographic processes such as those disclosed herein. As shownin FIG. 6A, when substrate layer 31 is stereolithographicallyfabricated, channels 33 may be recessed in one or both surfaces thereofto receive intermediate conductive elements 20′. Thus, the exposedsurfaces of intermediate conductive elements 20′ may be recessedrelative to the surfaces of substrate layer 31 or substantially flushtherewith. When stereolithography is used to fabricate substrate layer31, the layer or layers of material are preferably deposited onto aflexible or fibrous matrix and become integral therewith, therebyimparting strength and some flexibility to the fabricated substratelayer 31.

When both intermediate conductive elements 20′ and substrate layer 31are stereolithographically fabricated, carrier substrates 30 that carryintermediate conductive elements 20′ on both surfaces thereof may befabricated by forming a first, bottom set of intermediate conductiveelements 20′ on a platform of a suitable stereolithography apparatus,forming substrate layer 31 over the first set of intermediate conductiveelements 20′, then forming a second, upper set of intermediateconductive elements 20′ on substrate layer 31. Any vias 36 that extendvertically through substrate layer 31 may be fabricated before, during,or after the fabrication of substrate layer 31. When both intermediateconductive elements 20′ and substrate layer 31 are fabricated by use ofstereolithography, the same stereolithographic technique and apparatusare preferably employed to fabricate intermediate conductive elements20′ and substrate layer 31. Accordingly, carrier substrate 30 need notbe moved between different stereolithographic apparatus duringfabrication thereof. However, the use of different stereolithographictechniques and apparatus to fabricate intermediate conductive elements20′ and substrate layer 31 are also within the scope of the presentinvention.

FIG. 7 schematically illustrates a multilayer carrier substrate 30′according to the present invention, which includes a plurality ofsuperimposed, contiguous, mutually adhered layers 31′ of dielectricmaterial and intermediate conductive elements 20′ that are each carriedby one or more of layers 31′. Intermediate conductive elements 20′ thatare carried by more than one layer 31′ and, thus, that extend along morethan one plane through carrier substrate 30′ include vias 36 along thelengths thereof. Vias 36 extend substantially vertically through throughholes 38′ formed in one or more layers 31′.

Intermediate conductive elements 20′, which are preferably fabricated bystereolithographic techniques such as those disclosed herein, eachinclude one layer or a plurality of superimposed, contiguous, mutuallyadhered layers of conductive material, such as a conductive elastomer(e.g., a thermoplastic conductive elastomer or a conductivephotopolymer) or a metal.

One or more layers 31′ of carrier substrate 30′ may also be fabricatedby stereolithographic techniques using a dielectric material. Whenstereolithography is used to fabricate layers 31′ of carrier substrate30′, each layer 31′ may be made by disposing dielectric material onto alayer of a flexible or fibrous matrix to impart strength and someflexibility to each fabricated substrate layer 31′.

When both intermediate conductive elements 20′ and substrate layer 31′are stereolithographically fabricated, a first, bottom set ofintermediate conductive elements 20′ may be formed on a platform of asuitable stereolithography apparatus, forming a first substrate layer31′ over or laterally adjacent to the first set of intermediateconductive elements 20′. The appropriate sequence of formingintermediate conductive elements 20′ and substrate layers 31′ thencontinues until a multilayer carrier substrate 30′ of desiredconfiguration has been fabricated. Any vias 36 that extend verticallythrough one or more substrate layers 31′ may be fabricated before,during, or after the fabrication of the substrate layers 31′. When bothintermediate conductive elements 20′ and substrate layers 31′ arefabricated by use of stereolithography, the same stereolithographictechnique and apparatus are preferably employed to fabricateintermediate conductive elements 20′ and substrate layers 31′.Accordingly, carrier substrate 30′ need not be moved between differentstereolithographic apparatus during fabrication thereof. However, theuse of different stereolithographic techniques and apparatus tofabricate intermediate conductive elements 20′ and substrate layers 31′are also within the scope of the present invention.

Turning now to FIGS. 8 and 9, packaged semiconductor devices thatinclude stereolithographically fabricated conductive elements are alsowithin the scope of the present invention.

FIG. 8 illustrates an exemplary semiconductor device package 3incorporating teachings of the present invention. Semiconductor devicepackage 3 includes a semiconductor device 10, illustrated as aleads-over-chip (LOC) type semiconductor die, leads 40 positioned overan active surface 14 of semiconductor device 10 proximate correspondingbond pads 12 on active surface 14, and intermediate conductive elements20″ disposed between leads 40 and bond pads 12 so as to establishelectrical communication therebetween. Leads 40 and active surface 14are electrically isolated from one another by way of one or moredielectric layers 42 disposed therebetween. Semiconductor device package3 may also include a package 50. While package 50 is illustrated ascovering substantially the entire semiconductor device 10 and theportions of leads 40 adjacent semiconductor device 10, package 50 mayonly enclose bond pads 12 and intermediate conductive elements 20″.

Intermediate conductive elements 20″ are stereolithographicallyfabricated structures that may include one layer or a plurality ofsuperimposed, contiguous, mutually adhered layers of a conductivematerial, such as a conductive elastomer or a metal. Dielectric layers42 and package 50 may also be fabricated by stereolithographictechniques.

With reference to FIG. 9, another embodiment of a semiconductor devicepackage 4 that incorporates teachings of the present invention isillustrated. Semiconductor device package 4 includes a semiconductordevice 10, illustrated as a LOC type semiconductor die, with bond pads12 on an active surface 14 thereof. Intermediate conductive elements20′″ communicate with selected bond pads 12 and extend laterally so asto reroute selected bond pads 12 to different lateral locations relativeto active surface 14. The laterally extending portions of intermediateconductive elements 20′″ are electrically isolated from active surface14 by way of a dielectric layer 42 positioned therebetween. Eachintermediate conductive element 20′″ includes a contact 26′″ at an endor along the length thereof. Contacts 26′″ are at least electricallyexposed through a protective layer 44 and may include integralconductive structures 28′″ or attached conductive structures 28′″, suchas solder bumps, protruding therefrom.

Intermediate conductive elements 20′″ are stereolithographicallyfabricated and may each include a single layer or a plurality ofsuperimposed, contiguous, mutually adhered layers of a conductivematerial, such as a conductive elastomer or a metal. Conductivestructures 28′″ protruding from intermediate conductive elements 20′″may also be stereolithographically fabricated from conductive material.In addition, dielectric layer 42 and protective layer 44 may befabricated from dielectric materials by use of stereolithographictechniques.

FIG. 10 illustrates yet another use of conductive elements according tothe present invention, wherein a packaged semiconductor device 60 withleads 62 extending therefrom is connected to a carrier substrate 30.Leads 62 are electrically connected to corresponding contact pads 32 ofcarrier substrate 30 by way of intermediate conductive elements 20″,such as those described above with reference to FIG. 8.

Of course, other semiconductor devices and semiconductor deviceassemblies that include stereolithographically fabricated conductiveelements are also within the scope of the present invention.

While the present invention has been disclosed in terms of certainpreferred embodiments, those of ordinary skill in the art will recognizeand appreciate that the invention is not so limited. Additions,deletions and modifications to the disclosed embodiments may be effectedwithout departing from the scope of the invention as claimed herein.Similarly, features from one embodiment may be combined with those ofanother while remaining within the scope-of the invention.

1. A semiconductor device assembly, comprising: a semiconductor devicecomponent including at least one contact; and at least one conductiveelement in electrical communication with the at least one contact, theat least one conductive element including a plurality of adjacent,mutually adhered regions.
 2. The semiconductor device assembly of claim1, wherein the at least one conductive element includes at least aportion that extends laterally relative to a plane within which at leastone of the semiconductor device and the at least one other semiconductordevice is disposed.
 3. The semiconductor device assembly of claim 1,wherein at least one region of the plurality of adjacent, mutuallyadhered regions comprises a polymer.
 4. The semiconductor deviceassembly of claim 1, wherein at least one region of the plurality ofadjacent, mutually adhered regions comprises metal.
 5. The semiconductordevice assembly of claim 1, further comprising: another semiconductordevice component including a corresponding bond pad in electricalcommunication with the at least one conductive element.
 6. Thesemiconductor device assembly of claim 5, further comprising: a carrierto which at least one of the semiconductor device component and theanother semiconductor device component is secured.
 7. The semiconductordevice assembly of claim 6, further comprising: at least one otherconductive element connecting at least one contact of at least one ofthe semiconductor devices to a contact of the carrier and comprising aplurality of adjacent, mutually adhered regions.
 8. The semiconductordevice assembly of claim 1, wherein the plurality of adjacent, mutuallyadhered regions comprises a plurality of superimposed, contiguous,mutually adhered layers.
 9. The semiconductor device assembly of claim1, wherein the plurality of adjacent, mutually adhered regions comprisethe same type of conductive material.
 10. The semiconductor deviceassembly of claim 9, wherein the at least one conductive elementcomprises a semiconductor device.
 11. A semiconductor device assembly,comprising: a first semiconductor device component including at leastone first contact; a second semiconductor device component including asecond contact corresponding to the at least one first contact; and atleast one conductive element extending between and facilitatingelectrical communication between the at least one first contact and thecorresponding second contact, the at least one conductive elementcomprising a plurality of adjacent, mutually adhered regions.
 12. Thesemiconductor device assembly of claim 11, wherein the at least oneconductive element includes at least a portion that extends laterallyrelative to a plane within which at least one of the first semiconductordevice and the second semiconductor device is disposed.
 13. Thesemiconductor device assembly of claim 11, wherein each region of theplurality of adjacent, mutually adhered regions comprises a same type ofmaterial as all of the other regions of the plurality of adjacent,mutually adhered regions.
 14. The semiconductor device assembly of claim11, wherein at least one region of the plurality of adjacent, mutuallyadhered regions comprises a polymer.
 15. The semiconductor deviceassembly of claim 11, wherein at least one region of the plurality ofadjacent, mutually adhered regions comprises a metal.
 16. Thesemiconductor device assembly of claim 11, wherein the plurality ofadjacent, mutually adhered regions comprises a plurality ofsuperimposed, contiguous, mutually adhered layers.
 17. The semiconductordevice assembly of claim 11, wherein the first semiconductor devicecomponent comprises a semiconductor device.
 18. The semiconductor deviceassembly of claim 17, wherein the second semiconductor device componentcomprises a semiconductor device.
 19. A conductive element forelectrically connecting two contacts of an electronic component to oneanother, comprising a plurality of adjacent, mutually adhered regions.20. The conductive element of claim 19, at least a portion of whichextends laterally.
 21. The conductive element of claim 19, wherein eachregion of the plurality of adjacent, mutually adhered regions comprisesa same type of material as all of the other regions of the plurality ofadjacent, mutually adhered regions.
 22. The conductive element of claim19, wherein at least one region of the plurality of adjacent, mutuallyadhered regions comprises a polymer.
 23. The conductive element of claim19, wherein at least one region of the plurality of adjacent, mutuallyadhered regions comprises a metal.
 24. The conductive element of claim19, wherein the plurality of adjacent, mutually adhered regionscomprises a plurality of superimposed, contiguous, mutually adheredlayers.